First time I’ve used this modeling software and was impressed. Working out NTSC Luminance timing logic is a big help after just a couple mins. 100Mhz clock on the FPGA so we can just count nanoseconds. Can export to Verilog after simulation. Most excellent #commodore #vicsrevenge

Progress this morning before the day job kicks in: I have an externally clocked VIC-20! Internal timing being driven my an ICE40 FPGA. It’s a couple cycles slow but getting there. Now to start on video signals. The math makes my brain hurt. More coffee #commodore #vicsrevenge

One of the very strange quirks about NTSC and PAL Composite video on VIC-20s is the half frame interlacing and the offset odd numbers you have to “count”. So how long exactly is each frame SUPPOSED to be… #commodore #vicsrevenge

Gonna have to build some sort of test bench jig if I’m going to have 32 leads connected to the VIC chip at once without it being a wire hot mess. Good news it the DreamSourceLab 32 channel analyzer arrived and took about 60 seconds to set up. #commodore

Well this is good, turns out I do know how to create a B&W PAL (and NTSC) Composite/S-Video signal from scratch. My timings aren’t quite right, but it’s close. Good first crack though. #commodore #VIC20hacking #learnallthethings