Michael Doornbos
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Back on the VIC chip FPGA replacement this evening after a needed break. Having to level shift both directions between the VIC-20(5V) and the FPGA(3.3V) is a recipe for a crazy breadboard mess. Working on tidying it up. Looking better already.#vicsrevenge #commodore

▸ Jul 21, 2022 ▸ Michael Doornbos ▸ 0 words

← Happy Thursday! #commodore Good grief, these are still waaayyy too long. I’m gonna have to break down and buy an IDC cable connector crimper. Until then, let’s get the VIC-20 memory map more organized in my Verilog shall we? #commodore →
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