Michael Doornbos
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Wait, everyone didn’t save their Trapper? I’m the only one? Huh.
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Jun 29, 2022
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Michael Doornbos
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← Designing composite video in FPGA for the 6560/1 VIC replacement project #vicsrevenge... this might be the most useful visualizer/synthesis tool I've ever seen. Load your Verilog and get a visual representation AND what amounts to a test bench setup. Brilliant! #FPGA #commodore
Taking a break from a VMWare certification to have a little Apple IIe fun. I don't have a color monitor (my Apple monitor is Green) so to get color I HAVE to use my capture setup. Works pretty well ;-) →
